Method for fabricating semiconductor device

ABSTRACT

A method for forming a polysilicon layer includes forming an amorphous silicon layer over a substrate, performing a first thermal treatment of the amorphous silicon layer by performing an implantation with a gas that includes silicon (Si), and performing a second thermal treatment on the thermally treated layer at a temperature higher than a temperature of the first thermal treatment.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No.10-2011-0045199, filed on May 13, 2011, which is incorporated herein byreference in its entirety.

BACKGROUND

1. Field

Exemplary embodiments of the present invention relate to a semiconductordevice fabrication technology, and more particularly, to a method forforming a polysilicon layer and a method for forming buried bit lines.

2. Description of the Related Art

When buried bit lines BBL are used in cells of a vertical transistorstructure, two cells may neighbor one buried bit line. For example, fora cell to be driven by a buried bit line, a One-Side Contact (OSC)process in which a contact is formed in any one side of an active regionwhile the other side of the active region is insulated.

In a cell having a vertical transistor structure formed through theone-side contact process, an active region includes a body isolated bytrenches and a pillar formed over the body. The buried bit lines BBLfill the trenches between bodies and word lines (or vertical gates) aredisposed adjacent to the sidewalls of pillars and extended in adirection crossing the buried bit lines BBL. Channels are formed in avertical direction using the word lines.

According to the one-side contact process, a portion of any one sidewallof a body, which is an active region, has to be exposed for connectionbetween the active region and a buried bit line BBL. To form theone-side contact, the trenches between the bodies are filled with agap-fill layer having a step height. As for the gap-fill layer, apolysilicon layer may be used.

However, a seam may occur during the formation of the polysilicon layerdue to narrow linewidth of the contact. The occurrence of the seamcauses lack of uniformity during an etch-back process where not only aliner oxide layer which is formed for insulation from the buried bitlines BBL but also the substrate under the trenches are damaged andcause formation of active punch in the substrate.

FIGS. 1A and 1B are Transmission Electron Microscopic (TEM) photographsillustrating results of the conventional technology.

FIG. 1A illustrates that the middle of the polysilicon layer is hollowdue to occurrences of seam.

FIG. 1B illustrates that the liner oxide layer and the substrate underthe trenches are damaged due to the occurrence of seam on thepolysilicon layer in FIG. 1A and that an active punch is formed thereby.

Therefore, when the polysilicon layer is formed, the polysilicon layershould be formed without a defect such as a seam.

SUMMARY

An embodiment of the present invention is directed to a method forfabricating a semiconductor device without a defect.

Another embodiment of the present invention is directed to a method forfabricating a semiconductor device in which an active punch is notformed when buried bit lines are formed.

In accordance with an embodiment of the present invention, a method forforming a polysilicon layer includes: forming an amorphous silicon layerover a substrate; performing a first thermal treatment by performing animplantation with a gas including silicon (Si); and performing a secondthermal treatment at a temperature higher than a temperature of thefirst thermal treatment.

In accordance with another embodiment of the present invention, a methodfor fabricating a semiconductor device includes: forming openings in asubstrate; forming an amorphous silicon layer filling the openings;performing a first thermal treatment on the amorphous silicon layerwhile performing an implantation with a gas that includes silicon (Si);and performing a second thermal treatment on the thermally treated layerat a temperature higher than a temperature of the first thermaltreatment.

In accordance with yet another embodiment of the present invention, amethod for forming buried bit lines of a semiconductor device includes:forming a plurality of bodies that are isolated from each other bytrenches by etching a substrate; forming an amorphous silicon layerfilling the bodies; crystallizing the amorphous silicon layer into apolysilicon layer by performing an implantation with a gas that includessilicon (Si) and performing a first thermal treatment; performing asecond thermal treatment on the crystallized layer at a temperaturehigher than a temperature of the first thermal treatment; forming afirst gap-fill layer filling a portion of each trench by etching thepolysilicon layer; forming a second gap-fill layer over the firstgap-fill layer so that the second gap-fill layer is disposed inside thetrench to form a protrusion over each body; forming an etch barrier overthe substrate including the protrusion; performing a tilt ionimplantation over the etch barrier; selectively removing a portion ofthe etch barrier that is not ion-implanted; and forming openings thateach open one sidewall of a respective body.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are Transmission Electron Microscopic (TEM) photographsshowing the problems of conventional technology.

FIGS. 2A to 2C are cross-sectional views illustrating a method forforming a polysilicon layer over a plane in accordance with anembodiment of the present invention.

FIGS. 3A to 3D are cross-sectional views illustrating a method forforming a polysilicon layer in a contact in accordance with anembodiment of the present invention.

FIGS. 4A to 4M are cross-sectional views illustrating a method forforming buried bit lines over a plane in accordance with an embodimentof the present invention.

FIGS. 5A and 5B are Transmission Electron Microscopic (TEM) photographsshowing a polysilicon layer formed in accordance with an embodiment ofthe present invention.

FIGS. 6A to 6E are cross-sectional views illustrating a process afterthe formation of buried bit lines.

DETAILED DESCRIPTION

Exemplary embodiments of the present invention will be described belowin more detail with reference to the accompanying drawings. The presentinvention may, however, be embodied in different forms and should not beconstrued as limited to the embodiments set forth herein. Rather, theseembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of the present invention tothose skilled in the art. Throughout the disclosure, like referencenumerals refer to like parts throughout the various figures andembodiments of the present invention.

The drawings are not necessarily to scale and in some instances,proportions may have been exaggerated in order to clearly illustratefeatures of the embodiments. When a first layer is referred to as being“on” a second layer or “on” a substrate, it not only refers to a casewhere the first layer is formed directly on the second layer or thesubstrate but also a case where a third layer exists between the firstlayer and the second layer or the substrate.

FIGS. 2A to 2C are cross-sectional views illustrating a method forforming a polysilicon layer over a plane in accordance with anembodiment of the present invention.

Referring to FIG. 2A, an amorphous silicon layer 102 is formed over asubstrate 101. The amorphous silicon layer 102 is formed at a lowtemperature to control the deposition rate thereof, where the lowtemperature tends to decrease the deposition rate. The amorphous siliconlayer 102 may be formed at a temperature of approximately 300° C. toapproximately 500° C.

Referring to FIG. 2B, a first thermal treatment is performed tocrystallize the amorphous silicon layer 102 into a polysilicon layer102A. Here, the first thermal treatment is performed while performingimplantation using silane (SiH₄) gas.

The first thermal treatment is performed to crystallize the amorphoussilicon layer 102 (see FIG. 2A) into a polysilicon layer 102A, where theamorphous silicon layer 102 is treated at the same temperature as thetemperature set for the deposition of the amorphous silicon layer 102,which ranges from approximately 300° C. to approximately 500° C., forapproximately 30 minutes to approximately 3 hours. Here, when the firstthermal treatment is performed where an implantation with silane (SiH₄)gas is performed, silicon elements penetrate into the fine poresgenerated during the crystallization so as to improve thecrystallization quality. Also, as hydrogen (H) and oxygen in theatmosphere react with each other, surface oxidation that may occurotherwise may be prevented during the crystallization.

Referring to FIG. 2C, a second thermal treatment is performed. Thesecond thermal treatment is performed to improve the stability of thepolysilicon layer 102A, which was obtained from the crystallizationperformed through the first thermal treatment, where the polysiliconlayer 102A is treated at a temperature ranging from approximately 600°C. to approximately 800° C. for approximately 20 minutes toapproximately 1 hour. During the second thermal treatment, variousbyproducts may be evaporated for removal, and the bonding between thesilicon elements filling the fine pores during the first thermaltreatment and the polysilicon layer 102A may be stabilized.

As described above, deposition profile of the amorphous polysiliconlayer 102 may be improved by forming the amorphous polysilicon layer 102at a low temperature to decrease the deposition rate, and the layerquality is improved through the first thermal treatment using silane(SiH₄) gas and the second thermal treatment that is performed at ahigher temperature than that of the first thermal treatment. In thisway, the polysilicon layer 102A preventing the formation of fine poresmay be prevented.

FIGS. 3A to 3D are cross-sectional views illustrating a method forforming a polysilicon layer inside a contact in accordance with anembodiment of the present invention.

Referring to FIG. 3A, an amorphous silicon layer 202 filling a contactof a desired depth is formed over a substrate 201 which includes thecontact. The amorphous silicon layer 202 is formed at a low temperatureto control the deposition rate, that is, to decrease the depositionrate. The amorphous silicon layer 202 may be formed at a temperatureranging from approximately 300° C. to approximately 500° C.

When the amorphous silicon layer 202 is formed at a low deposition rateat the temperature of approximately 300° C. to approximately 500°,deposition profile thereof is improved to thereby prevent seam or voidfrom being formed. On the other hand, when the amorphous silicon layer202 is formed at a temperature of approximately 600° C. or higher, theamorphous silicon layer 202 may be crystallized into a polysilicon layeras soon as it is deposited and a seam or void may be formed as the fastcrystallization promotes clogging up an opening of the contact. However,according to an example, by depositing he amorphous silicon layer 202 ata temperature ranging from approximately 300° C. to approximately 500°C., quick crystallization and the formation of a seam or void areprevented.

Referring to FIG. 3B, a first thermal treatment is performed tocrystallize the amorphous silicon layer 202 into a polysilicon layer202A. Here, the first thermal treatment is performed by performing animplantation with silane (SiH₄) gas.

The first thermal treatment is performed to crystallize the amorphoussilicon layer 202 (see FIG. 2A) into a polysilicon layer 202A, where theamorphous silicon layer 202 is treated at the same temperature as thetemperature set for the deposition of the amorphous silicon layer 202,which ranges from approximately 300° C. to approximately 500° C., forapproximately 30 minutes to approximately 3 hours. Here, when the firstthermal treatment is performed by performing an implantation with silane(SiH₄) gas, the formation of a gap or defect caused by grain growth maybe prevented. Also, silicon elements penetrate into the fine poresformed during the crystallization so as to improve the crystallizationquality. Also, as hydrogen (H) and oxygen in the atmosphere react witheach other, surface oxidation that may occur otherwise during thecrystallization may be prevented.

Referring to FIG. 3C, a second thermal treatment is performed. Thesecond thermal treatment is performed to improve the stability of thepolysilicon layer 202A, which was obtained from the crystallizationperformed through the first thermal treatment, and the second thermaltreatment is performed at a temperature ranging from approximately 600°C. to approximately 800° C. for approximately 20 minutes toapproximately 1 hour. During the second thermal treatment, variousbyproducts are evaporated for being removed, and the bonding between thesilicon elements filling the fine pores during the first thermaltreatment and the polysilicon layer 202A may be stabilized.

As described above, a deposition profile of the amorphous polysiliconlayer 202 may be improved by forming the amorphous polysilicon layer 202at a low temperature to decrease the deposition rate, and the layerquality is improved through the first thermal treatment using silane(SiH₄) gas and the second thermal treatment that is performed at ahigher temperature than that of the first thermal treatment. In thisway, the polysilicon layer 202A where the formation of fine pores isprevented may be formed.

Referring to FIG. 3D, the polysilicon layer 202A is etched to partiallyfill a contact. To this end, the surface of the substrate 201 istargeted for a planarization process, and then an etch-back process isperformed so that the polysilicon layer 202A fills a portion of thecontact. Here, the planarization process may be a Chemical MechanicalPolishing (CMP) process.

The method for forming the seam-free or void-free polysilicon layer inthe contact may be applied to diverse such as forming contact plugs orburied bit lines. According to an exemplary embodiment of the presentinvention, the method for forming the seam-free or void-free polysiliconlayer is applied to a method for forming buried bit lines.

FIGS. 4A to 4M are cross-sectional views illustrating a method forforming buried bit lines over a plane in accordance with an embodimentof the present invention.

Referring to FIG. 4A, bodies 402 are formed by a hard mask layer pattern404 as an etch barrier and etching a substrate 401. The bodies 402 areisolated from each other by trenches 403. A liner oxide layer 405 isformed as an insulation layer over the substrate structure including thebodies 402. The liner oxide layer 405 includes an oxide layer such as asilicon oxide layer.

An amorphous silicon layer 406 gap-filling the trenches 403 is formedover the liner oxide layer 405. The amorphous silicon layer 406 is usedas a gap-fill layer for forming an opening that opens a portion of asidewall of a body subsequently. The amorphous silicon layer 406 may beformed free of seam and may form an opening at a desired position andprotect the substrate 401 from being damaged in a subsequent etch-backprocess.

To this end, the amorphous silicon layer 406 is formed at a lowtemperature to control the deposition rate, that is, to decrease thedeposition rate. The amorphous silicon layer 406 may be formed at atemperature ranging from approximately 300° C. to approximately 500° C.

When the amorphous silicon layer 406 is formed at a low deposition rateat a temperature of approximately 300° C. to approximately 500° C.,deposition profile thereof is improved so as to prevent an occurrence ofa seam or void. On the other hand, when the amorphous silicon layer 406is deposited at a temperature higher than approximately 600° C., it maybe crystallized as soon as it is deposited, where the fastcrystallization may promote clogging up of an opening of a contact.However, according to an example, by depositing the amorphous siliconlayer 406 at a temperature of approximately 300° C. to approximately500° C., the quick crystallization and the formation of a seam or voidare prevented.

Referring to FIG. 4B, a first thermal treatment is performed tocrystallize the amorphous silicon layer 406 into a polysilicon layer406A. Here, the first thermal treatment is performed by performing animplantation with silane (SiH₄) gas.

In crystallizing the amorphous silicon layer 406 (see FIG. 4A) into apolysilicon layer 406A, the first thermal treatment is performed at thesame temperature that the amorphous silicon layer 406 is deposited,which is between approximately 300° C. and approximately 500° C., forapproximately 30 minutes to approximately 3 hours. Here, when the firstthermal treatment is performed by performing an implantation with silane(SiH₄) gas, the formation of a gap or defect caused from grain growthmay be prevented due to the implantation of silicon. Also, as thesilicon elements penetrate into fine pores formed during thecrystallization, the crystallization quality may be improved, and whenthe hydrogen (H) and oxygen in the atmosphere react with each other,surface oxidation that may be caused during the crystallization may beprevented.

Referring to FIG. 4C, a second thermal treatment is performed. Thesecond thermal treatment is performed to improve the stability of thepolysilicon layer 406A which is obtained from the crystallizationthrough the first thermal treatment. The second thermal treatment isperformed at a temperature of approximately 600° C. to approximately800° C. for approximately 2 minutes to approximately 1 hour. Diversebyproducts are evaporated and removed through the second thermaltreatment, and the bond between the silicon elements implanted duringthe first thermal treatment and the polysilicon layer 406A may bestabilized.

As described above, the deposition profile of the amorphous siliconlayer 406 is improved by forming the amorphous silicon layer 406 at alow temperature and decreasing the deposition rate, and the layerquality is improved as well through the first thermal treatment usingsilane (SiH₄) gas and the second thermal treatment that is performed ata higher temperature than the first thermal treatment. Also, the seam orvoid-free polysilicon layer 406A may be formed. This will be describedin detail in reference to the Transmission Electron Microscopic (TEM)photographs of FIGS. 5A and 5B.

Referring to FIG. 4D, a first gap-fill layer pattern 407 is formed byetching the polysilicon layer 406A to fill a portion of a contact. Tothis end, a planarization is performed targeting the surface of the hardmask layer pattern 404, and then an etch-back process is performed sothat the polysilicon layer 406A fills a portion of a contact. Theplanarization may be a Chemical Mechanical Polishing (CMP) process.

After the etch-back process, the first gap-fill layer pattern 407provides a first recess R1. During the CMP process, the liner oxidelayer 405 over the hard mask layer pattern 404 may be polished out. Inpolishing out the liner oxide layer 405 over the hard mask layer pattern404, the hard mask layer pattern 404 and a liner oxide layer pattern405A covering both sidewalls of each trench 403 remain. The liner oxidelayer pattern 405A also covers the bottom of each trench 403.

Subsequently, the liner oxide layer pattern 405A is thinned through awet etch process. Therefore, the liner oxide layer pattern 405Aremaining on the sidewalls of the first recess R1 becomes thinner thanthe liner oxide layer pattern 405A surrounding/covering the firstgap-fill layer pattern 407.

Referring to FIG. 4E, a liner nitride layer 408 is formed over thesubstrate structure including the first gap-fill layer pattern 407 as aninsulation layer. The liner nitride layer 408 includes a nitride layersuch as a silicon nitride layer.

Referring to FIG. 4F, the liner nitride layer 408 is etched. As aresult, a liner nitride layer pattern 408A is formed. Subsequently, thefirst gap-fill layer pattern 407 is recessed to a desired depth by usingthe liner nitride layer pattern 408A as an etch barrier. As a result, asecond recess R2 is formed. The first gap-fill layer pattern with thesecond recess R2 formed therein is denoted with a reference numeral‘407A.’

As the first gap-fill layer pattern 407A with the second recess

R2 is recessed due to the formation of the second recess R2, the lineroxide layer pattern 405A is exposed between the liner nitride layerpattern 408A and the first gap-fill layer pattern 407A with the secondrecess R2.

Referring to FIG. 4G, a metal nitride layer is formed conformally overthe substrate structure including the second recess R2. Subsequently,spacers 409 are formed by performing a spacer etch process. The spacers409 are formed on both sidewalls of each body 402, that is, bothsidewalls of the second recess R2. The spacers 409 may include atitanium nitride layer (TiN).

A second gap-fill layer 410 is formed to gap-fill the second recess R2where the spacers 409 are formed. The second gap-fill layer 410 includesan oxide layer. The second gap-fill layer 410 includes a Spin-OnDielectric (SOD) layer.

Referring to FIG. 4H, after the second gap-fill layer 410 is planarized,the second gap-fill layer 410 is etched back. As a result, a recessedsecond gap-fill layer pattern 410A is formed.

Subsequently, an etch barrier 411 is formed over the substrate structureincluding the second gap-fill layer pattern 410A. The etch barrier 411includes an undoped polysilicon layer.

Referring to FIG. 41, a tilt ion implantation process 412 is performed.The tilt ion implantation process 412 is a process of implanting ions ofa dopant at a desired angle. Here, the amount of energy is controlled toimplant the dopant into a portion of the etch barrier 411.

The tilt ion implantation process 412 is performed at a desired angle,which ranges from approximately 5° to approximately 30°. A portion ofion beam is shadowed by the hard mask layer pattern 404. Therefore, aportion of the etch barrier 411 is doped and the other portion of theetch barrier 411 remains undoped. For example, the ion-implanted dopantmay be a P-type dopant. More specifically, the ion-implanted dopant maybe boron, and a dopant source used for ion-implanting boron may be boronfluorine (BF₂). As a result, a portion of the etch barrier 411 remainsundoped. The portion remaining undoped is a portion adjacent to the leftside of the hard mask layer pattern 404.

The portion formed on the upper surface of the hard mask layer pattern404 of the etch barrier 411 through the tilt ion implantation process412 of the dopant and the portion adjacent to the right side of the hardmask layer pattern 404 become a doped etch barrier 411A, which is dopedwith the dopant. The etch barrier 411 which is not implanted with thedopant becomes an undoped etch barrier 411B.

Referring to FIG. 4J, the undoped etch barrier 411B is removed. Here,the polysilicon used as an etch barrier has different etch rateaccording to whether the portion is doped with the dopant or not.Particularly, the undoped polysilicon which is not implanted with thedopant has a fast wet etch rate. Therefore, the undoped etch barrier411B may be removed through a wet etch process or a wet cleaning processby using a chemical which has a high etch selectivity and is capable ofwet-etching the undoped polysilicon.

When the undoped etch barrier 411B is removed as described above, thedoped etch barrier 411A remains.

Referring to FIG. 4K, one of the spacers 409 is removed. Morespecifically, the spacer 409 between the doped etch barrier 411A isremoved. As a result, a gap 413 is formed. The spacer is removed througha wet etch process. As a result, one spacer 409A in the opposite sideremains.

Referring to FIG. 41L, a cleaning process is performed to expose aportion of any one sidewall of each body 402.

The cleaning process includes a wet cleaning process. A wet cleaningprocess is performed using hydrofluoride (HF), buffered oxide etchant(BOE) and the like. When the wet cleaning process is performed, aportion of the liner oxide layer pattern 405A is removed so as to forman opening 414 that exposes the body 402. When the opening 414 isformed, the second gap-fill layer pattern 410A is removed together.

As described above, the hard mask layer pattern 404, the liner oxidelayer pattern 405A, and the liner nitride layer pattern 408A arecollectively referred to as an insulation layer. Here, the insulationlayer provides the opening 414 that exposes a portion of any onesidewall of each body 402.

Referring to FIG. 4M, the remaining spacer 409A and the doped etchbarrier 411A are removed. When the doped etch barrier 411A is removed,the first gap-fill layer pattern 407A with the second recess R2 isremoved together.

Subsequently, a junction region is formed on the portion of a sidewallof the body exposed by the opening 414, and buried bit lines are formedto fill a portion of each trench 403 as coupled with the junctionregion. Also, a bit line protective layer and an inter-layer dielectriclayer may be formed over the buried bit lines, which will be describedin detail later with reference to FIGS. 6A to 6E.

FIGS. 5A and 5B are Transmission Electron Microscopic (TEM) photographsshowing a polysilicon layer formed in accordance with an embodiment ofthe present invention.

Referring to FIGS. 5A and 5B, it may be seen that when the polysiliconlayer, that is, the first gap-fill layer pattern obtained from theetch-back process is formed, a seam or void does not occur and the lineroxide layer and the substrate are not damaged.

FIGS. 6A to 6E are cross-sectional views illustrating a process afterthe formation of buried bit lines. FIGS. 6A to 6E simultaneously showthe cross sections of the FIG. 4M structure after forming buried bitlines along lines B-B′ and C-C′.

Referring to FIG. 6A, buried bit lines 416 filling a portion of eachtrench 403 are formed over the liner oxide layer pattern 405A, and a bitline protective layer 417 is formed along the profile of the entirestructure including the buried bit lines 416. Subsequently, a firstinter-layer dielectric layer 418 is formed over the substrate structureincluding the bit line protective layer 417. Subsequently, the firstinter-layer dielectric layer 418 is planarized until the surface of thehard mask layer pattern 404 is exposed.

Referring to FIG. 6B, word line trenches 419 are formed. To form theword line trenches 419, a photoresist layer pattern, which is not shownin the drawing, is used. The first inter-layer dielectric layer 418 isetched to a desired depth by using the photoresist pattern as an etchbarrier. When the first inter-layer dielectric layer 418 is etched, thehard mask layer pattern 404 and the bodies 402 are etched to a desireddepth as well. As a result, pillars 402B are formed over the etchedbodies 402A. The etched bodies 402A and the pillars 402B become activeregions. The etched bodies 402A are portions where junction regions 415are formed. The etched bodies 402A have a shape of lines extended in thesame direction as the buried bit lines 416. The pillars 402B are formedover the etched bodies 402A to be extended vertically. The pillars 402Bare formed for respective cells. The remaining first inter-layerdielectric layer 418 having a thickness R1 serves as an isolation layerbetween the buried bit lines 416 and vertical word lines.

Referring to FIG. 6C, a word line conductive layer 421 is formed togap-fill the word line trenches 419 (see FIG. 6B). subsequently, aplanarization process and an etch-back process are performed until theword line conductive layer 421 remains at a height gap-filling a portionof each word line trench 419. A gate insulation layer 420 is formedbefore the word line conductive layer 421 is formed.

Referring to FIG. 6D, spacers 422 are formed by performing an etch-backprocess after a nitride layer is deposited. The word line conductivelayer 421 is etched using the spacers 422 as etch barriers. As a result,vertical word lines 421A are formed adjacent to the sidewalls of thepillars 402B. The vertical word lines 421A also serve as vertical gates.According to another embodiment of the present invention, the verticalword lines 421A may be formed to couple neighboring vertical gates witheach other after circular vertical gates surrounding each pillar 402Bare formed. The vertical word lines 421A are formed in a directioncrossing the buried bit lines 416.

Referring to FIG. 6E, a second inter-layer dielectric layer 423 isformed over the substrate structure including the vertical word lines421A.

The upper portion of each pillar 402B is exposed by performing a storagenode contact etch process. As a result, storage node contact plugs (SNC)425 are formed. Drains 424 may be formed by performing an ionimplantation before the storage node contact plugs 425 are formed. As aresult, vertical channel transistors each including a drain 424, ajunction region 415, and a vertical word line 421A are formed. Avertical channel is formed by the vertical word line 421A between thedrain 424 and the junction region 415. The junction regions 415 becomethe source for the vertical channel transistors.

Storage nodes 426 are formed over the storage node contact plugs 425.The storage nodes 426 may have a cylindrical shape.

According to another embodiment, the storage nodes 426 may have a pillarshape or a concave shape. Subsequently, a dielectric layer and an upperelectrode are formed.

The method for fabricating a semiconductor device in accordance with anembodiment of the present invention improves a deposition profile byforming an amorphous silicon layer at a low temperature and decreasing adeposition rate, improves the layer quality through a first thermaltreatment using a silane gas and a second thermal treatment performed ata higher temperature than that of the first thermal treatment, preventsfine pores, and forms a seam-free and void-free polysilicon layer.Therefore, an active punch may be prevented from being generated whenburied bit lines BBL are formed.

While the present invention has been described with respect to thespecific embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirit and scope of the invention as defined in the followingclaims.

What is claimed is:
 1. A method for forming a polysilicon layer,comprising: forming an amorphous silicon layer over a substrate;performing a first thermal treatment of the amorphous silicon layer tocrystallize the amorphous silicon layer into a polysilicon layer whileperforming an implantation directly onto the amorphous silicon with agas that includes silicon (Si); and performing a second thermaltreatment on the polysilicon layer at a temperature higher than atemperature of the first thermal treatment.
 2. The method of claim 1,wherein the gas including silicon (Si) comprises silane (SiH₄).
 3. Themethod of claim 1, wherein the amorphous silicon layer is formed at atemperature ranging from approximately 300° C. to approximately 500° C.4. The method of claim 1, wherein the first thermal treatment isperformed at the same temperature that the amorphous silicon layer isformed.
 5. The method of claim 1, wherein the first thermal treatment isperformed at a temperature ranging from approximately 300° C. toapproximately 500° C.
 6. The method of claim 1, wherein the secondthermal treatment is performed at a temperature ranging fromapproximately 600° C. to approximately 800° C.
 7. The method of claim 1,wherein the second thermal treatment evaporates byproducts remainingafter the first thermal treatment.
 8. A method for fabricating asemiconductor device, comprising: forming openings in a substrate;forming an amorphous silicon layer filling the openings; performing afirst thermal treatment on the amorphous silicon layer to crystallizethe amorphous silicon layer into a polysilicon layer while performing animplantation directly onto the amorphous silicon with a gas thatincludes silicon (Si), wherein the first thermal treatment is performedat substantially the same temperature that the amorphous silicon layeris formed; and performing a second thermal treatment on the polysiliconlayer at a temperature higher than a temperature of the first thermaltreatment.
 9. The method of claim 8, wherein the gas comprises silane(SiH₄).
 10. The method of claim 8, wherein the amorphous silicon layeris formed at a temperature ranging from approximately 300° C. toapproximately 500° C.
 11. A method for forming buried bit lines of asemiconductor device, the method comprising: forming a plurality ofbodies that are isolated from each other by trenches by etching asubstrate; forming an amorphous silicon layer filling the bodies;crystallizing the amorphous silicon layer into a polysilicon layer byperforming an implantation with a gas that includes silicon (Si) andperforming a first thermal treatment; performing a second thermaltreatment on the crystallized layer at a temperature higher than atemperature of the first thermal treatment; forming a first gap-filllayer filling a portion of each trench by etching the polysilicon layer;forming a second gap-fill layer over the first gap-fill layer so thatthe second gap-fill layer is disposed inside the trench to form aprotrusion over each body; forming an etch barrier over the substrateincluding the protrusion; performing a tilt ion implantation over theetch barrier; selectively removing a portion of the etch barrier that isnot ion-implanted; and forming openings that each open one sidewall of arespective body.
 12. The method of claim 11, wherein the gas comprisessilane (SiH₄).
 13. The method of claim 11, wherein the amorphous siliconlayer is formed at a temperature ranging from approximately 300° C. toapproximately 500° C.
 14. The method of claim 11, wherein the firstthermal treatment is performed at the same temperature that theamorphous silicon layer is formed.
 15. The method of claim 11, whereinthe first thermal treatment is performed at a temperature ranging fromapproximately 300° C. to approximately 500° C.
 16. The method of claim11, wherein the second thermal treatment is performed at a temperatureranging from approximately 600° C. to approximately 800° C.
 17. Themethod of claim 11, wherein the etch barrier is an undoped polysiliconlayer.
 18. The method of claim 11, further comprising: forming buriedbit lines that are coupled with the openings and each fill a portion ofa respective trench after the forming of the openings.